In a non-volatile (NV) memory, such as a NAND type flash memory or a 3D vertical gate (3DVG) NAND flash memory, memory cells are usually managed in a hierarchical structure. The basic programming unit in a NV memory is a page, in which a group of memory cells may be programmed together during a programming process. One or more pages may be controlled by a word line (WL), which applies a voltage to control gates of the memory cells in the page. In a conventional non-3DVG NV memory, a WL may control only one page. However, in a 3DVG NV memory, a WL may control multiple pages, such as 4 or 8 pages, stacked vertically one on another. As used herein, a group of pages controlled by the same WL is referred to as a WL section (note that for a conventional non-3DVG NV memory, a WL section may be equivalent to one page). Further, a group of WL sections, such as 32 or 64 WL sections, may form a block, which constitutes a unit for erasing. That is, all memory cells in a block are erased together in one erasing operation.
A WL, a page, or a memory cell in a NV memory can be damaged due to various reasons, so that the pages controlled by the damaged WL, the damaged page, or the damaged memory cell may become inaccessible or not able to store data, and thus become useless. For example, in a 3DVG NV memory, a WL may be damaged due to WL open or a WL short. A WL section having a damaged WL, damaged page, or damaged memory cell is referred to herein as a damaged WL section. Conventionally, in a NV memory, a logical-to-physical (L2P) mapping is designed at a block level. That is, each block in the NV memory is assigned a L2P mapping. Therefore, it may be difficult to bypass a damaged WL section in a block. Consequently, a block with damaged WL sections would be marked as a bad block and thus not usable to store data. That is, one damaged WL section in a block, which may comprise 32 or 64 WL sections, would cause the entire block to be useless, even if other WL sections in the block are not damaged. This results in wasted storage capacity. On the other hand, if the L2P mapping is designed at a page level (i.e., each page being assigned a L2P mapping), the amount of RAM required for L2P mapping may be significantly increased, which could significantly increase cost.